18 lines
248 B
Plaintext
18 lines
248 B
Plaintext
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module verilog_test1 (clk,
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in1,
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out1);
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input clk;
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input in1;
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output out1;
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wire extra_wire;
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wire n1;
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BUF_X1 buf1 (.A(in1),
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.Z(n1));
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INV_X1 extra_inv (.A(extra_wire));
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DFF_X1 reg1 (.D(n1),
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.CK(clk),
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.Q(out1));
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endmodule
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