Jaehyun KimandClaude f192996a42 Update golden files for upstream bias_pins feature ...

Upstream added bias pin type recognition, changing VNB/VPB pin
direction from "unknown" to "bias" in liberty output. Update 9
golden .ok files to match.

Co-Authored-By: Claude <[email protected]>
Signed-off-by: Jaehyun Kim <[email protected]>

2026-04-02 12:42:08 +09:00

..

test

Update golden files for upstream bias_pins feature

2026-04-02 12:42:08 +09:00

Verilog.i

update copyright

2026-03-10 14:57:45 -07:00

Verilog.tcl

update copyright

2026-03-10 14:57:45 -07:00

VerilogLex.ll

string squash

2026-03-28 19:13:35 -07:00

VerilogParse.yy

string squash

2026-03-28 19:13:35 -07:00

VerilogReader.cc

string squash

2026-03-28 19:13:35 -07:00

VerilogReaderPvt.hh

string squash

2026-03-28 19:13:35 -07:00

VerilogScanner.hh

string squash

2026-03-28 19:13:35 -07:00

VerilogWriter.cc

fix to exclude bias pins from timing graph

2026-04-02 00:56:38 +00:00