2026-02-13 11:19:09 +01:00
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|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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|
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|
Endpoint: out1 (output port clocked by clk1)
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|
Path Group: clk1
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|
Path Type: max
|
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|
|
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|
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|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 0.00 clock network delay (ideal)
|
|
|
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
|
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
|
|
|
0.00 0.08 ^ out1 (out)
|
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|
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|
0.08 data arrival time
|
|
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|
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|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
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|
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|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 clock reconvergence pessimism
|
|
|
|
|
-3.00 7.00 output external delay
|
|
|
|
|
7.00 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
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|
7.00 data required time
|
|
|
|
|
-0.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
6.92 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
|
|
|
Path Group: clk2
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
|
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
|
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
|
|
|
10.08 data arrival time
|
|
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|
|
|
|
|
|
|
20.00 20.00 clock clk2 (rise edge)
|
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|
0.00 20.00 clock network delay (ideal)
|
|
|
|
|
0.00 20.00 clock reconvergence pessimism
|
|
|
|
|
20.00 ^ reg3/CK (DFF_X1)
|
|
|
|
|
-0.04 19.96 library setup time
|
|
|
|
|
19.96 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
19.96 data required time
|
|
|
|
|
-10.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
9.88 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: out1 (output port clocked by clk1)
|
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|
|
|
Path Group: clk1
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|
Path Type: max
|
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|
|
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|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 0.00 clock network delay (ideal)
|
|
|
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
|
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
|
|
|
0.00 0.08 ^ out1 (out)
|
|
|
|
|
0.08 data arrival time
|
|
|
|
|
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 clock reconvergence pessimism
|
|
|
|
|
-3.00 7.00 output external delay
|
|
|
|
|
7.00 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
7.00 data required time
|
|
|
|
|
-0.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
6.92 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
|
|
|
Path Group: clk2
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
|
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
|
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
|
|
|
10.08 data arrival time
|
|
|
|
|
|
|
|
|
|
20.00 20.00 clock clk2 (rise edge)
|
|
|
|
|
0.00 20.00 clock network delay (ideal)
|
|
|
|
|
0.00 20.00 clock reconvergence pessimism
|
|
|
|
|
20.00 ^ reg3/CK (DFF_X1)
|
|
|
|
|
-0.04 19.96 library setup time
|
|
|
|
|
19.96 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
19.96 data required time
|
|
|
|
|
-10.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
9.88 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
2026-02-23 03:50:23 +01:00
|
|
|
No differences found.
|
2026-02-13 11:19:09 +01:00
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: out1 (output port clocked by clk1)
|
|
|
|
|
Path Group: clk1
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 0.00 clock network delay (ideal)
|
|
|
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
|
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
|
|
|
0.00 0.08 ^ out1 (out)
|
|
|
|
|
0.08 data arrival time
|
|
|
|
|
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 clock reconvergence pessimism
|
|
|
|
|
-3.00 7.00 output external delay
|
|
|
|
|
7.00 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
7.00 data required time
|
|
|
|
|
-0.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
6.92 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
|
|
|
Path Group: clk2
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
|
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
|
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
|
|
|
10.08 data arrival time
|
|
|
|
|
|
|
|
|
|
20.00 20.00 clock clk2 (rise edge)
|
|
|
|
|
0.00 20.00 clock network delay (ideal)
|
|
|
|
|
0.00 20.00 clock reconvergence pessimism
|
|
|
|
|
20.00 ^ reg3/CK (DFF_X1)
|
|
|
|
|
-0.04 19.96 library setup time
|
|
|
|
|
19.96 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
19.96 data required time
|
|
|
|
|
-10.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
9.88 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
2026-02-23 03:50:23 +01:00
|
|
|
No differences found.
|
|
|
|
|
No differences found.
|
|
|
|
|
No differences found.
|
2026-02-13 11:19:09 +01:00
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: out1 (output port clocked by clk1)
|
|
|
|
|
Path Group: clk1
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 0.00 clock network delay (ideal)
|
|
|
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
|
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
|
|
|
0.00 0.08 ^ out1 (out)
|
|
|
|
|
0.08 data arrival time
|
|
|
|
|
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 clock reconvergence pessimism
|
|
|
|
|
-3.00 7.00 output external delay
|
|
|
|
|
7.00 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
7.00 data required time
|
|
|
|
|
-0.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
6.92 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
|
|
|
Path Group: clk2
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
|
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
|
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
|
|
|
10.08 data arrival time
|
|
|
|
|
|
|
|
|
|
20.00 20.00 clock clk2 (rise edge)
|
|
|
|
|
0.00 20.00 clock network delay (ideal)
|
|
|
|
|
0.00 20.00 clock reconvergence pessimism
|
|
|
|
|
20.00 ^ reg3/CK (DFF_X1)
|
|
|
|
|
-0.04 19.96 library setup time
|
|
|
|
|
19.96 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
19.96 data required time
|
|
|
|
|
-10.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
9.88 slack (MET)
|
|
|
|
|
|
|
|
|
|
|
2026-02-23 03:50:23 +01:00
|
|
|
No differences found.
|
|
|
|
|
No differences found.
|
test: Fix post-merge build errors and regolden .ok files
After merging upstream changes, fix all build errors in C++ test files
and regolden Tcl test golden files to match updated code output.
Build fixes:
- dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use
EXPECT_NEAR for uninitialized subnormal float comparison
- liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed
LibertyBuilder() default constructor in #if 0
- liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder()
call to use sta_->debug()/report(); wrap old visitor tests in #if 0
- search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr
comparison (now returns std::string&)
- search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock
tests to expect throw (API now requires linked network)
Tcl test fixes:
- Remove calls to removed APIs: report_path_end_header/footer, report_path_end2
from 6 search test scripts; regolden their .ok files
- Regolden .ok files for liberty (15), graph (1), network (8),
parasitics (3), sdc (3), util (2), verilog (8) modules to reflect
upstream format changes (timing arcs output, pin ordering, spacing)
All 6103 tests now pass.
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-03-11 09:11:08 +01:00
|
|
|
No differences found.
|
|
|
|
|
No differences found.
|
|
|
|
|
No differences found.
|
2026-02-20 07:32:08 +01:00
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: out1 (output port clocked by clk1)
|
2026-02-13 11:19:09 +01:00
|
|
|
Path Group: clk1
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
2026-02-20 07:32:08 +01:00
|
|
|
0.00 0.00 clock clk1 (rise edge)
|
2026-02-13 11:19:09 +01:00
|
|
|
0.00 0.00 clock network delay (ideal)
|
2026-02-20 07:32:08 +01:00
|
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
|
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
|
|
|
0.00 0.08 ^ out1 (out)
|
|
|
|
|
0.08 data arrival time
|
2026-02-13 11:19:09 +01:00
|
|
|
|
2026-02-20 07:32:08 +01:00
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 clock reconvergence pessimism
|
|
|
|
|
-3.00 7.00 output external delay
|
|
|
|
|
7.00 data required time
|
2026-02-13 11:19:09 +01:00
|
|
|
---------------------------------------------------------
|
2026-02-20 07:32:08 +01:00
|
|
|
7.00 data required time
|
|
|
|
|
-0.08 data arrival time
|
2026-02-13 11:19:09 +01:00
|
|
|
---------------------------------------------------------
|
2026-02-20 07:32:08 +01:00
|
|
|
6.92 slack (MET)
|
2026-02-13 11:19:09 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
|
|
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
|
|
|
|
Path Group: clk2
|
|
|
|
|
Path Type: max
|
|
|
|
|
|
|
|
|
|
Delay Time Description
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
10.00 10.00 clock clk1 (rise edge)
|
|
|
|
|
0.00 10.00 clock network delay (ideal)
|
|
|
|
|
0.00 10.00 ^ reg1/CK (DFF_X1)
|
|
|
|
|
0.08 10.08 v reg1/Q (DFF_X1)
|
|
|
|
|
0.00 10.08 v reg3/D (DFF_X1)
|
|
|
|
|
10.08 data arrival time
|
|
|
|
|
|
|
|
|
|
20.00 20.00 clock clk2 (rise edge)
|
|
|
|
|
0.00 20.00 clock network delay (ideal)
|
|
|
|
|
0.00 20.00 clock reconvergence pessimism
|
|
|
|
|
20.00 ^ reg3/CK (DFF_X1)
|
|
|
|
|
-0.04 19.96 library setup time
|
|
|
|
|
19.96 data required time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
19.96 data required time
|
|
|
|
|
-10.08 data arrival time
|
|
|
|
|
---------------------------------------------------------
|
|
|
|
|
9.88 slack (MET)
|
|
|
|
|
|
|
|
|
|
|