2019-11-08 16:45:03 +01:00
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# 3 corners with +/- 10% derating example
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2019-03-21 22:17:25 +01:00
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define_corners ss tt ff
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2019-11-08 16:45:03 +01:00
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read_liberty -corner ss example1_slow.lib
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2019-03-21 22:17:25 +01:00
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read_liberty -corner tt example1_typ.lib
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2019-11-08 16:45:03 +01:00
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read_liberty -corner ff example1_fast.lib
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2019-03-21 18:48:50 +01:00
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read_verilog example1.v
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link_design top
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set_timing_derate -early 0.9
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2019-03-22 01:08:48 +01:00
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set_timing_derate -late 1.1
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2019-03-21 18:48:50 +01:00
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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2019-03-21 22:17:25 +01:00
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# report all corners
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2019-03-21 18:48:50 +01:00
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report_checks -path_delay min_max
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2019-03-21 22:17:25 +01:00
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# report typical corner
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report_checks -corner tt
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