example5

2019-03-21 17:08:48 -07:00 · 2019-03-21 17:08:48 -07:00 · 601143cec3
parent 892324dfd9
commit 601143cec3
1 changed files with 1 additions and 1 deletions
--- a/examples/example5.tcl
+++ b/examples/example5.tcl
@ -6,7 +6,7 @@ read_liberty -corner ff  example1_fast.lib
 read_verilog example1.v
 link_design top
 set_timing_derate -early 0.9
-set_timing_derate -early 1.1
+set_timing_derate -late  1.1
 create_clock -name clk -period 10 {clk1 clk2 clk3}
 set_input_delay -clock clk 0 {in1 in2}
 # report all corners