OpenRAM/compiler/base
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
..
contact.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
design.py Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
geometry.py Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
hierarchy_design.py Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
hierarchy_layout.py Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
hierarchy_spice.py Fix print check regression 2018-10-15 13:23:31 -07:00
lef.py Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
path.py Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
pin_layout.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
route.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
utils.py Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
vector.py Fix Future Warning for real 2018-10-10 15:58:16 -07:00
verilog.py Move last few modules to base dir 2018-02-09 10:29:37 -08:00
wire.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00