Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering

2018-11-11 07:22:13 -08:00

..

__init__.py

Fix check for missing simulator type in characterizer

2018-10-25 09:08:56 -07:00

charutils.py

Fix module import names for python3. Rename parse function to something meaningful.

2018-06-29 09:45:07 -07:00

delay.py

Convert port index lists to three simple lists.

2018-11-08 12:19:40 -08:00

functional.py

Convert port index lists to three simple lists.

2018-11-08 12:19:40 -08:00

lib.py

added another VLSI logo and fixed control port numbering

2018-11-11 07:22:13 -08:00

setup_hold.py

Updating ms_flop removal.

2018-09-13 11:40:24 -07:00

simulation.py

Convert port index lists to three simple lists.

2018-11-08 12:19:40 -08:00

stimuli.py

Add ngspice equivalents of RUNLVL

2018-10-24 10:31:27 -07:00

trim_spice.py

Fixed merge conflicts with sram.py

2018-10-22 17:29:14 -07:00

worst_case.py

Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation

2018-10-09 17:44:28 -07:00