Jesse Cirimelli-Low fa27d647d2 Flask directory upload POC, embed datasheet.info in html comment for parser reuse

2018-11-13 17:29:43 -08:00

..

base

Change channel router to route from bottom up to simplify code.

2018-11-11 12:25:53 -08:00

bitcells

Merge branch 'dev' into multiport_layout

2018-11-08 18:00:28 -08:00

characterizer

added another VLSI logo and fixed control port numbering

2018-11-11 07:22:13 -08:00

datasheet

Flask directory upload POC, embed datasheet.info in html comment for parser reuse

2018-11-13 17:29:43 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

modules

Fixed small bugs with new port index stuff and layout.

2018-11-08 17:40:22 -08:00

pgates

Adjust ptx positions in precharge to be under the bl rail

2018-11-09 10:26:15 -08:00

router

Expand blocked pins to neighbor grid cells.

2018-11-09 14:25:10 -08:00

tests

Comment out regress CI debug code

2018-11-10 13:44:36 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Add magic/netgen to example config

2018-11-07 13:54:00 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

options.py

Fix openram_temp directory

2018-10-06 08:08:01 -07:00

sram_1bank.py

Change channel router to route from bottom up to simplify code.

2018-11-11 12:25:53 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

sram_base.py

Fixed small bugs with new port index stuff and layout.

2018-11-08 17:40:22 -08:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

added area to datasheet

2018-11-08 21:30:17 -08:00