Jesse Cirimelli-Low f9eae3fb80 route bias pisn

2021-05-24 02:42:04 -07:00

..

base

route bias pisn

2021-05-24 02:42:04 -07:00

bitcells

Update copyright year.

2021-01-22 11:23:28 -08:00

characterizer

Removed measurement check which conflicts with multiport memories

2021-04-21 15:53:27 -07:00

custom

Add noninverting logic function to custom decoder cells.

2021-04-22 16:13:54 -07:00

datasheet

Merge branch 'dev' into automated_analytical_model

2021-02-01 01:49:45 -08:00

drc

Update copyright year.

2021-01-22 11:23:28 -08:00

example_configs

Add vdd/gnd pins to the side.

2021-05-03 15:14:15 -07:00

gdsMill

Merge branch 'dev' into laptop_checkpoint

2021-05-07 19:06:17 -07:00

modules

route bias pisn

2021-05-24 02:42:04 -07:00

pgates

uncomment test (passing)

2021-05-03 13:08:04 -07:00

router

route bias pisn

2021-05-24 02:42:04 -07:00

sram

Merge branch 'dev' into laptop_checkpoint

2021-05-07 19:06:17 -07:00

tests

Update golden tests for verilog

2021-05-06 19:56:22 -07:00

verify

route bias pisn

2021-05-24 02:42:04 -07:00

debug.py

Skywater changes.

2021-03-22 15:48:14 -07:00

gen_stimulus.py

Update copyright year.

2021-01-22 11:23:28 -08:00

globals.py

Merge branch 'dev' into laptop_checkpoint

2021-05-03 12:53:31 -07:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Update copyright year.

2021-01-22 11:23:28 -08:00

options.py

Merge branch 'dev' into laptop_checkpoint

2021-04-23 22:50:23 -07:00

printGDS.py

Add printGDS script to aid debugging things.

2020-12-02 11:52:38 -08:00

processGDS.py

Make default no magnification to text. PEP8 Cleanup

2020-12-09 11:42:28 -08:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Update copyright year.

2021-01-22 11:23:28 -08:00

view_profile.py

Update copyright year.

2021-01-22 11:23:28 -08:00