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channel_route.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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contact.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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custom_cell_properties.py
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support multi cell wide precharge cells
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2021-04-23 22:49:29 -07:00 |
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custom_layer_properties.py
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Abstracted LEF added. Params for array wordline layers.
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2021-04-21 11:04:01 -07:00 |
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delay_data.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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design.py
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remove debug lines and merge
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2021-02-09 20:53:23 -08:00 |
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errors.py
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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geometry.py
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Merge remote-tracking branch 'bvhoof/dev' into dev
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2021-03-01 12:16:26 -08:00 |
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graph_util.py
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Added debug measurements along main delay paths in SRAM. WIP.
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2020-11-17 12:43:17 -08:00 |
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hierarchy_design.py
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Reimplement trim options (except on unit tests).
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2021-04-07 16:07:56 -07:00 |
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hierarchy_layout.py
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route bias pisn
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2021-05-24 02:42:04 -07:00 |
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hierarchy_spice.py
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Reimplement trim options (except on unit tests).
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2021-04-07 16:07:56 -07:00 |
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lef.py
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Must transitively cut blockages until no more.
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2021-05-05 13:44:06 -07:00 |
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pin_layout.py
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Abstracted LEF added. Params for array wordline layers.
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2021-04-21 11:04:01 -07:00 |
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power_data.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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route.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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utils.py
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remove debug lines and merge
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2021-02-09 20:53:23 -08:00 |
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vector.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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verilog.py
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Fix Verilog module typo. Adjust RBL route.
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2021-05-06 14:32:47 -07:00 |
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wire.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wire_path.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wire_spice_model.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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