Jesse Cirimelli-Low f9eae3fb80 route bias pisn

2021-05-24 02:42:04 -07:00

..

channel_route.py

Update copyright year.

2021-01-22 11:23:28 -08:00

contact.py

Update copyright year.

2021-01-22 11:23:28 -08:00

custom_cell_properties.py

support multi cell wide precharge cells

2021-04-23 22:49:29 -07:00

custom_layer_properties.py

Abstracted LEF added. Params for array wordline layers.

2021-04-21 11:04:01 -07:00

delay_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

design.py

remove debug lines and merge

2021-02-09 20:53:23 -08:00

errors.py

Add exception errors file

2020-04-08 16:55:45 -07:00

geometry.py

Merge remote-tracking branch 'bvhoof/dev' into dev

2021-03-01 12:16:26 -08:00

graph_util.py

Added debug measurements along main delay paths in SRAM. WIP.

2020-11-17 12:43:17 -08:00

hierarchy_design.py

Reimplement trim options (except on unit tests).

2021-04-07 16:07:56 -07:00

hierarchy_layout.py

route bias pisn

2021-05-24 02:42:04 -07:00

hierarchy_spice.py

Reimplement trim options (except on unit tests).

2021-04-07 16:07:56 -07:00

lef.py

Must transitively cut blockages until no more.

2021-05-05 13:44:06 -07:00

pin_layout.py

Abstracted LEF added. Params for array wordline layers.

2021-04-21 11:04:01 -07:00

power_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

route.py

Update copyright year.

2021-01-22 11:23:28 -08:00

utils.py

remove debug lines and merge

2021-02-09 20:53:23 -08:00

vector.py

Update copyright year.

2021-01-22 11:23:28 -08:00

verilog.py

Fix Verilog module typo. Adjust RBL route.

2021-05-06 14:32:47 -07:00

wire_path.py

Update copyright year.

2021-01-22 11:23:28 -08:00

wire_spice_model.py

Update copyright year.

2021-01-22 11:23:28 -08:00

wire.py

Update copyright year.

2021-01-22 11:23:28 -08:00