mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.

2020-11-20 16:56:07 -08:00

..

and2_dec.py

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

and3_dec.py

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

and4_dec.py

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

bank_select.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

bank.py

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

bitcell_array.py

Rework bitcells.

2020-11-13 10:07:40 -08:00

bitcell_base_array.py

Get vdd/gnd from properties if it is defined.

2020-11-16 10:14:37 -08:00

col_cap_array.py

Fix bounding box of cap arrays

2020-11-20 16:54:53 -08:00

column_mux_array.py

Fix various typos and errors

2020-11-13 16:04:07 -08:00

control_logic.py

Move pin name mapping to layout class.

2020-11-16 11:04:03 -08:00

delay_chain.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

dff_array.py

Move pin name mapping to layout class.

2020-11-16 11:04:03 -08:00

dff_buf_array.py

Move pin name mapping to layout class.

2020-11-16 11:04:03 -08:00

dff_buf.py

Small bug fixes related to new name mapping.

2020-11-16 13:42:42 -08:00

dff_inv_array.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

dff_inv.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

dummy_array.py

Add bl/br pins to dummy array

2020-11-12 12:38:09 -08:00

global_bitcell_array.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

hierarchical_decoder.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

hierarchical_predecode2x4.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

hierarchical_predecode3x8.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

hierarchical_predecode4x16.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

hierarchical_predecode.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

local_bitcell_array.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

orig_bitcell_array.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

port_address.py

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

port_data.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

precharge_array.py

Fix pbitcell erros

2020-11-13 15:55:55 -08:00

replica_bitcell_array.py

Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.

2020-11-20 16:56:07 -08:00

replica_column.py

Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.

2020-11-20 16:56:07 -08:00

row_cap_array.py

Fix bounding box of cap arrays

2020-11-20 16:54:53 -08:00

sense_amp_array.py

Fix pbitcell erros

2020-11-13 15:55:55 -08:00

tri_gate_array.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

wordline_buffer_array.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

wordline_driver_array.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

write_driver_array.py

Fix pbitcell erros

2020-11-13 15:55:55 -08:00

write_mask_and_array.py

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00