luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
f4389bdd8f64044485a79fd4626bb322b64f7a0e
OpenRAM/compiler/tests
T
History
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
2018-09-13 12:53:35 -07:00
..
golden
Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files.
2018-09-06 22:51:34 -07:00
00_code_format_check_test.py
resolved variable name error in 00_code_format test
2018-08-15 03:33:33 -07:00
01_library_drc_test.py
Remove extra conversion to list
2018-07-11 12:07:37 -07:00
02_library_lvs_test.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
03_contact_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_path_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_ptx_1finger_nmos_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_ptx_1finger_pmos_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_ptx_3finger_nmos_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_ptx_3finger_pmos_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_ptx_4finger_nmos_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_ptx_4finger_pmos_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
03_wire_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pbitcell_test.py
Change options in pbitcell test to be global again.
2018-09-05 10:59:41 -07:00
04_pinv_1x_beta_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pinv_1x_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pinv_2x_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pinv_10x_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pinvbuf_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pnand2_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pnand3_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_pnor2_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
04_precharge_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
04_single_level_column_mux_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
05_bitcell_array_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
05_pbitcell_array_test.py
Add sram_config class. Rename port variables for better description.
2018-08-31 12:03:28 -07:00
06_hierarchical_decoder_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
06_hierarchical_predecode2x4_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
06_hierarchical_predecode3x8_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
07_single_level_column_mux_array_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
08_precharge_array_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
08_wordline_driver_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
09_sense_amp_array_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
10_write_driver_array_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
11_dff_array_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
11_dff_buf_array_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
11_dff_buf_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
11_dff_inv_array_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
11_dff_inv_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
12_tri_gate_array_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
13_delay_chain_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
14_replica_bitline_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
16_control_logic_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
19_bank_select_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
19_multi_bank_test.py
Add sram_config class. Rename port variables for better description.
2018-08-31 12:03:28 -07:00
19_psingle_bank_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
19_single_bank_test.py
Add sram_config class. Rename port variables for better description.
2018-08-31 12:03:28 -07:00
20_psram_1bank_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
20_sram_1bank_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
20_sram_2bank_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
20_sram_4bank_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
21_hspice_delay_test.py
Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay)
2018-09-06 18:40:21 -07:00
21_hspice_setuphold_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
21_ngspice_delay_test.py
Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay)
2018-09-06 18:40:21 -07:00
21_ngspice_setuphold_test.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
22_pex_test.py
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
22_sram_func_test.py
Modify unit tests to reset options during init_openram so
2018-07-10 16:39:32 -07:00
23_lib_sram_model_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
23_lib_sram_prune_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
23_lib_sram_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
24_lef_sram_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
25_verilog_sram_test.py
Cleanup some items with new sram_config. Update unit tests accordingly.
2018-09-04 10:47:24 -07:00
30_openram_test.py
Close output log in test 30 to avoid warning
2018-07-26 14:01:40 -07:00
config_20_freepdk45.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
config_20_scn3me_subm.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
config_20_scn4m_subm.py
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
out.log
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
regress.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
sram1_TT_5p0V_25C.lib
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
sram1.gds
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
sram1.lef
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
sram1.sp
Add sketch for power grid routing code
2018-08-29 15:34:16 -07:00
testutils.py
Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done.
2018-09-10 19:33:59 -07:00