Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array

2018-07-17 15:01:31 -07:00

..

bank_select.py

Consolidate metal pitch rules to new design class

2018-07-09 15:42:46 -07:00

bank.py

Single bank working except for channel routing error in 4-way case.

2018-07-17 14:40:04 -07:00

bitcell_array.py

simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations

2018-05-31 17:39:51 -07:00

bitcell.py

changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit

2018-05-22 14:16:51 -07:00

control_logic.py

Convert bank to use create_bus routines.

2018-07-16 14:13:41 -07:00

delay_chain.py

Add new power supplies to delay chain

2018-07-16 10:19:52 -07:00

dff_array.py

Add vdd/gnd pins to dff_array

2018-07-17 15:01:31 -07:00

dff_buf_array.py

Add M3 pins on dff_buf array

2018-04-11 12:09:15 -07:00

dff_buf.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

dff_inv_array.py

Add bank_sel to bank_select module as input.

2018-03-23 08:13:39 -07:00

dff_inv.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

dff.py

Add dff_buf for buffered flop arrays.

2018-03-04 16:13:10 -08:00

hierarchical_decoder.py

Push create bus functions down into layout class.

2018-07-10 10:06:59 -07:00

hierarchical_predecode2x4.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode3x8.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode.py

Fix spacing between adjacent decoders

2018-07-17 15:01:16 -07:00

ms_flop_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

ms_flop.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

precharge_array.py

Route precharge_array vdd in M3

2018-04-04 13:49:55 -07:00

replica_bitcell.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

replica_bitline.py

Add new supplies to RBL and control logic

2018-07-16 12:58:15 -07:00

sense_amp_array.py

Fix sense amp spacing after modifying index to be increment by one.

2018-06-29 15:30:17 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Consolidate metal pitch rules to new design class

2018-07-09 15:42:46 -07:00

tri_gate_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Move supply to M3 in wordline driver

2018-04-11 16:23:45 -07:00

write_driver_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00