OpenRAM/compiler/pgates
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
..
column_mux.py uncomment test (passing) 2021-05-03 13:08:04 -07:00
pand2.py Update copyright year. 2021-01-22 11:23:28 -08:00
pand3.py Update copyright year. 2021-01-22 11:23:28 -08:00
pand4.py Update copyright year. 2021-01-22 11:23:28 -08:00
pbuf.py Update copyright year. 2021-01-22 11:23:28 -08:00
pbuf_dec.py Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00
pdriver.py Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
pgate.py Update copyright year. 2021-01-22 11:23:28 -08:00
pinv.py Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
pinv_dec.py Update copyright year. 2021-01-22 11:23:28 -08:00
pinvbuf.py Update copyright year. 2021-01-22 11:23:28 -08:00
pnand2.py Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
pnand3.py Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
pnand4.py Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
pnor2.py Update copyright year. 2021-01-22 11:23:28 -08:00
precharge.py 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
ptristate_inv.py Update copyright year. 2021-01-22 11:23:28 -08:00
ptx.py Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
pwrite_driver.py Update copyright year. 2021-01-22 11:23:28 -08:00
wordline_driver.py Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00