OpenRAM/compiler
mrg e16f44cc81 Update lib file with external supply names 2021-05-26 15:34:32 -07:00
..
base Update lib file with external supply names 2021-05-26 15:34:32 -07:00
bitcells Update copyright year. 2021-01-22 11:23:28 -08:00
characterizer Update lib file with external supply names 2021-05-26 15:34:32 -07:00
custom Add noninverting logic function to custom decoder cells. 2021-04-22 16:13:54 -07:00
datasheet Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
drc Update copyright year. 2021-01-22 11:23:28 -08:00
example_configs Add vdd/gnd pins to the side. 2021-05-03 15:14:15 -07:00
gdsMill Add error with zero length labels on GDS write. 2021-05-05 13:44:31 -07:00
modules Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
pgates Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
router Add commented save npz file for intern 2021-05-06 17:14:27 -07:00
sram Typo in wmask supply variable 2021-05-26 15:24:31 -07:00
tests Add Xyce tests 2021-05-21 12:04:26 -07:00
verify Add destination file as dot file 2021-05-18 14:54:13 -07:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Skywater changes. 2021-03-22 15:48:14 -07:00
gen_stimulus.py Update copyright year. 2021-01-22 11:23:28 -08:00
globals.py Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
openram.py Update copyright year. 2021-01-22 11:23:28 -08:00
options.py Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
printGDS.py Add printGDS script to aid debugging things. 2020-12-02 11:52:38 -08:00
processGDS.py Make default no magnification to text. PEP8 Cleanup 2020-12-09 11:42:28 -08:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Update copyright year. 2021-01-22 11:23:28 -08:00
view_profile.py Update copyright year. 2021-01-22 11:23:28 -08:00