Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.		2019-05-07 00:52:27 -07:00
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contact.py	Added corner information for analytical power estimation.	2019-03-04 19:27:53 -08:00
design.py	Added initial graph for correct naming	2019-04-19 01:27:06 -07:00
geometry.py	Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.	2018-11-16 11:48:41 -08:00
graph_util.py	Added quality improvements to graph: improved naming, auto vdd/gnd removal	2019-04-29 23:57:25 -07:00
hierarchy_design.py	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
hierarchy_layout.py	Return empty set instead of a list.	2019-04-01 15:59:57 -07:00
hierarchy_spice.py	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
lef.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
pin_layout.py	Fix instersection bug. Improve primary and secondary pin algo.	2018-12-04 16:53:04 -08:00
route.py	Convert all contacts to use the sram_factory	2019-01-16 16:56:06 -08:00
utils.py	Allow multiple must-connect pins with the same label.	2018-11-07 13:05:13 -08:00
vector.py	Fix Future Warning for real	2018-10-10 15:58:16 -07:00
verilog.py	Remove tabs	2019-01-11 14:16:57 -08:00
wire.py	Change path to wire_path for Anaconda package conflict	2019-01-25 15:07:56 -08:00
wire_path.py	Change path to wire_path for Anaconda package conflict	2019-01-25 15:07:56 -08:00