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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
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d30f05a1ae6dd70eb3e5a13afc13d685c85c60ca
OpenRAM/technology/sky130/modules
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mrg bbfccd1e00 Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
..
sky130_bitcell_array.py
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
sky130_bitcell_base_array.py
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
sky130_bitcell.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_col_cap_array.py
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
sky130_col_cap.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_corner.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_dummy_array.py
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
sky130_dummy_bitcell.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_internal.py
fix bitcell array opc errors
2021-12-14 22:15:27 -08:00
sky130_replica_bitcell_array.py
fix bl routing in rba
2022-05-19 21:45:48 -07:00
sky130_replica_bitcell.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
sky130_replica_column.py
single port rba passing lvs
2022-03-07 13:45:50 -08:00
sky130_row_cap_array.py
remove add_mod in sky130
2021-12-22 15:51:49 -08:00
sky130_row_cap.py
Initial commit of sky130 config files
2021-10-04 15:16:28 -07:00
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