OpenRAM/compiler/pgates
Matt Guthaus d2ca2efdbe Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
..
pand2.py Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
pbuf.py Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
pgate.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
pinv.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
pinvbuf.py Add copy power pin function 2018-10-08 09:56:39 -07:00
pnand2.py Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
pnand3.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
pnor2.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
precharge.py Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
ptx.py Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
single_level_column_mux.py Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00