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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00
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cf63499e769d3b3f9174f2d47a73aeb40e21d55c
OpenRAM/technology/freepdk45/sp_lib
T
History
mrg cf63499e76 Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
..
cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
cell_6t.sp
update freepdk bitcell for pex
2020-08-17 17:47:43 -07:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
dummy_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
dummy_cell_6t.sp
change Qbar to Q_bar in freepdk45 bitcells
2020-08-04 15:21:54 -07:00
replica_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_6t.sp
Modify replica cell spice in FreePDK45 to short Qbar to vdd
2018-11-05 11:42:42 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
write_driver.sp
Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.
2018-02-01 05:38:48 -08:00
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