OpenRAM/compiler
Matt Guthaus ce94366a1d Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
..
base Remove diagonal routing bug. Cleanup. 2018-11-02 14:57:40 -07:00
bitcells Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
characterizer Add fixed seed to functional test during unit tests. Skip non-working tests after fixed seed. 2018-11-03 10:53:09 -07:00
datasheet moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
drc Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
gdsMill Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
modules Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
pgates Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
router Remove diagonal routing bug. Cleanup. 2018-11-02 14:57:40 -07:00
tests Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
verify Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Makefile Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
debug.py Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
example_config_freepdk45.py Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
example_config_scn4m_subm.py Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
gen_stimulus.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
globals.py Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
openram.py Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
options.py Fix openram_temp directory 2018-10-06 08:08:01 -07:00
sram.py Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
sram_1bank.py Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
sram_2bank.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
sram_4bank.py Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
sram_base.py Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
sram_config.py Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00