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bank.py
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Changed the analytical delay model to accept multiport options. Little substance to the values generated.
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2018-10-26 00:08:13 -07:00 |
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bank_select.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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bitcell_array.py
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Changed the analytical delay model to accept multiport options. Little substance to the values generated.
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2018-10-26 00:08:13 -07:00 |
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control_logic.py
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Change RBL size to 50% of row size.
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2018-10-11 10:39:24 -07:00 |
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delay_chain.py
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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dff.py
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Remove ms_flop and replace with dff. Might break setup_hold tests.
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2018-09-13 11:02:28 -07:00 |
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dff_array.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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dff_buf.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_buf_array.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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dff_inv.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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dff_inv_array.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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hierarchical_decoder.py
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Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.
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2018-10-20 12:54:12 -07:00 |
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hierarchical_predecode.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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hierarchical_predecode2x4.py
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Converted all submodules to use _bit notation instead of [bit]
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2018-10-11 09:53:08 -07:00 |
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hierarchical_predecode3x8.py
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Converted all submodules to use _bit notation instead of [bit]
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2018-10-11 09:53:08 -07:00 |
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multibank.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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precharge_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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replica_bitline.py
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Merge branch 'dev' into supply_routing
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2018-10-20 14:29:19 -07:00 |
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sense_amp.py
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Fixed spacing in golden lib files. Added column mux into analytical model.
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2018-10-24 00:16:26 -07:00 |
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sense_amp_array.py
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Fixed spacing in golden lib files. Added column mux into analytical model.
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2018-10-24 00:16:26 -07:00 |
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single_level_column_mux_array.py
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Fixed spacing in golden lib files. Added column mux into analytical model.
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2018-10-24 00:16:26 -07:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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wordline_driver.py
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Converted all submodules to use _bit notation instead of [bit]
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2018-10-11 09:53:08 -07:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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