mirror of https://github.com/VLSIDA/OpenRAM.git
Flatten and simplify 1rw 1r bitcell. Move bitcell vias to M3 if rotation is limited. Simplify replica bitcell vdd routing. |
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|---|---|---|
| .. | ||
| cell_1rw_1r.gds | ||
| cell_6t.gds | ||
| dff.gds | ||
| replica_cell_1rw_1r.gds | ||
| replica_cell_6t.gds | ||
| sense_amp.gds | ||
| tri_gate.gds | ||
| write_driver.gds | ||