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OpenRAM/technology/scn4m_subm/sp_lib
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mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 		2020-11-13 10:07:40 -08:00
..
cell_1rw.sp Rework bitcells. 2020-11-13 10:07:40 -08:00
cell_2rw.sp Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
cell_6t.st0 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
dff.sp Added scn4m_subm. 2018-09-13 12:53:35 -07:00
dummy_cell_1rw.sp Rework bitcells. 2020-11-13 10:07:40 -08:00
dummy_cell_2rw.sp Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
replica_cell_1rw.sp Rework bitcells. 2020-11-13 10:07:40 -08:00
replica_cell_2rw.sp Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
sense_amp.sp Added scn4m_subm. 2018-09-13 12:53:35 -07:00
tri_gate.sp Added scn4m_subm. 2018-09-13 12:53:35 -07:00
write_driver.sp Remove unnecessary footer in write driver 2019-08-01 08:59:41 -07:00