OpenRAM/compiler/custom
mrg 03e1b9c50d Clean up custom cells 2020-10-08 14:22:09 -07:00
..
and2_dec.py Change s8 to sky130 2020-06-12 14:23:26 -07:00
and3_dec.py Change s8 to sky130 2020-06-12 14:23:26 -07:00
and4_dec.py Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
dff.py Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
inv_dec.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
nand2_dec.py Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
nand3_dec.py Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
nand4_dec.py Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
s8_bitcell.py Clean up custom cells 2020-10-08 14:22:09 -07:00
s8_col_cap_array.py no wl for col end 2020-10-08 03:34:16 -07:00
s8_col_end.py Clean up custom cells 2020-10-08 14:22:09 -07:00
s8_corner.py Clean up custom cells 2020-10-08 14:22:09 -07:00
s8_dummy_bitcell.py no wl for col end 2020-10-08 03:34:16 -07:00
s8_internal.py Clean up custom cells 2020-10-08 14:22:09 -07:00
s8_replica_bitcell.py Clean up custom cells 2020-10-08 14:22:09 -07:00
s8_row_cap_array.py fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
s8_row_end.py fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
tri_gate.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00
write_driver.py Thin-cell decoder changes. 2020-05-29 10:36:07 -07:00