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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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c1411f422776bd5ea3de2b2cbb73898fa665a858
OpenRAM/compiler/pgates
T
History
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations
2019-04-09 01:56:32 -07:00
..
pand2.py
Added updated analytical characterization with combined models
2019-04-02 01:09:31 -07:00
pbuf.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pdriver.py
Added check to pdriver for 0 fanout which can break compute_sizes.
2019-04-03 17:53:28 -07:00
pgate.py
Convert pgates to use ptx through the factory
2019-01-16 16:30:31 -08:00
pinv.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
pinvbuf.py
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
pnand2.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
pnand3.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
pnor2.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
precharge.py
Convert pgates to use ptx through the factory
2019-01-16 16:30:31 -08:00
ptx.py
Change path to wire_path for Anaconda package conflict
2019-01-25 15:07:56 -08:00
single_level_column_mux.py
Added more accurate bitline delay capacitance estimations
2019-04-09 01:56:32 -07:00
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