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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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c07e20cbe4d6f2cca60b7fc836fd493e0ce433fc
OpenRAM/technology/scn4m_subm
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mrg cddb16dabc Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
..
gds_lib
Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver.
2019-08-08 15:49:23 -07:00
mag_lib
Flatten pbitcell_1 too
2020-06-02 09:31:43 -07:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sp_lib
Remove unnecessary footer in write driver
2019-08-01 08:59:41 -07:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
tf
Add Metal3/Via3/Metal4 on right gds layers
2019-09-03 15:28:20 -07:00
__init__.py
Move DRC/LVS/PEX tools to tech file.
2019-11-29 12:01:33 -08:00
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