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base
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Remove diagonal routing bug. Cleanup.
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2018-11-02 14:57:40 -07:00 |
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bitcells
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Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
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2018-11-01 12:29:49 -07:00 |
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characterizer
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Merge branch 'dev' into multiport_characterization
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2018-11-05 10:40:29 -08:00 |
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datasheet
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moved flask_table warning from sram.py to datasheet_gen.py
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2018-10-18 09:58:19 -07:00 |
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drc
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Moving wide metal spacing to routing grid level
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2018-10-15 09:59:16 -07:00 |
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gdsMill
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Fixed merge conflicts with sram.py
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2018-10-22 17:29:14 -07:00 |
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modules
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Fixed drc issues with replica bitline test.
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2018-11-02 17:16:41 -07:00 |
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pgates
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Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell.
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2018-10-18 07:05:47 -07:00 |
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router
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Remove diagonal routing bug. Cleanup.
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2018-11-02 14:57:40 -07:00 |
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tests
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Unskipped functional tests and increases the number of ports on pbitcell functional tests.
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2018-11-05 14:56:22 -08:00 |
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verify
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Remove old setup.tcl and edit one in tech dir
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2018-10-20 15:20:15 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Remove options from example config files
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2018-11-05 12:47:47 -08:00 |
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example_config_scn4m_subm.py
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Remove options from example config files
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2018-11-05 12:47:47 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Fixed merge conflicts with sram.py
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2018-10-22 17:29:14 -07:00 |
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openram.py
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Merge branch 'dev' into supply_routing
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2018-10-20 14:29:19 -07:00 |
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options.py
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Fix openram_temp directory
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2018-10-06 08:08:01 -07:00 |
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sram.py
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Fixed merge conflicts with sram.py
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2018-10-22 17:29:14 -07:00 |
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sram_1bank.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_4bank.py
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Converted all submodules to use _bit notation instead of [bit]
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2018-10-11 09:53:08 -07:00 |
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sram_base.py
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Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
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2018-10-30 22:19:26 -07:00 |
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sram_config.py
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
ff169fcb2b