Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.		2018-11-01 12:29:49 -07:00
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bitcell.py	Merge branch 'multiport' into supply_routing	2018-10-11 09:56:38 -07:00
bitcell_1rw_1r.py	Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.	2018-10-26 00:08:13 -07:00
pbitcell.py	Changed the analytical delay model to accept multiport options. Little substance to the values generated.	2018-10-26 00:08:13 -07:00
replica_bitcell.py	Move replica bitcells to new bitcells subdir	2018-10-24 09:06:29 -07:00
replica_bitcell_1rw_1r.py	Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.	2018-11-01 12:29:49 -07:00
replica_pbitcell.py	Move replica bitcells to new bitcells subdir	2018-10-24 09:06:29 -07:00