OpenRAM/compiler/modules
Hunter Nichols 0a26e40022 Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
..
bank.py Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
bank_select.py Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
bitcell_array.py Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
control_logic.py Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
delay_chain.py Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
dff.py Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
dff_array.py Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
dff_buf.py Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
dff_buf_array.py Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
dff_inv.py Merge branch 'dev' into multiport_characterization 2018-11-19 15:42:48 -08:00
dff_inv_array.py Remove dff_inv since we can just use dff_buf 2018-11-28 10:42:22 -08:00
hierarchical_decoder.py Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
hierarchical_predecode.py Fix col address dff spacing from bank. 2018-11-29 09:54:29 -08:00
hierarchical_predecode2x4.py Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
hierarchical_predecode3x8.py Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
multibank.py Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
precharge_array.py Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
replica_bitline.py Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
sense_amp.py Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
sense_amp_array.py Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
single_level_column_mux_array.py Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00
tri_gate.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
tri_gate_array.py Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
wordline_driver.py Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
write_driver.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
write_driver_array.py Remove extra X in instance names 2018-11-27 12:02:53 -08:00