mirror of https://github.com/VLSIDA/OpenRAM.git
185 lines
7.2 KiB
Python
185 lines
7.2 KiB
Python
import debug
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import design
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from tech import drc,parameter
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from math import log
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from vector import vector
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from globals import OPTS
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from pinv import pinv
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class dff_buf(design.design):
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"""
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This is a simple buffered DFF. The output is buffered
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with two inverters, of variable size, to provide q
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and qbar. This is to enable driving large fanout loads.
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"""
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unique_id = 1
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def __init__(self, inv1_size=2, inv2_size=4, name=""):
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if name=="":
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name = "dff_buf_{0}".format(dff_buf.unique_id)
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dff_buf.unique_id += 1
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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# This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
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# This causes a DRC in the pinv which assumes min width rails. This ensures the output
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# contact does not violate spacing to the rail in the NMOS.
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debug.check(inv1_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
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debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
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self.inv1_size=inv1_size
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self.inv2_size=inv2_size
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.width = self.dff.width + self.inv1.width + self.inv2.width
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self.height = self.dff.height
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self.place_instances()
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self.route_wires()
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self.add_layout_pins()
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self.DRC_LVS()
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def add_modules(self):
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from importlib import reload
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c = reload(__import__(OPTS.dff))
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self.mod_dff = getattr(c, OPTS.dff)
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self.dff = self.mod_dff("dff")
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self.add_mod(self.dff)
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self.inv1 = pinv(size=self.inv1_size,height=self.dff.height)
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self.add_mod(self.inv1)
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self.inv2 = pinv(size=self.inv2_size,height=self.dff.height)
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self.add_mod(self.inv2)
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def add_pins(self):
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self.add_pin("D")
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self.add_pin("Q")
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self.add_pin("Qb")
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self.add_pin("clk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_instances(self):
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self.dff_inst=self.add_inst(name="dff_buf_dff",
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mod=self.dff)
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self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
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self.inv1_inst=self.add_inst(name="dff_buf_inv1",
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mod=self.inv1)
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self.connect_inst(["qint", "Qb", "vdd", "gnd"])
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self.inv2_inst=self.add_inst(name="dff_buf_inv2",
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mod=self.inv2)
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self.connect_inst(["Qb", "Q", "vdd", "gnd"])
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def place_instances(self):
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# Add the DFF
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self.dff_inst.place(vector(0,0))
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# Add INV1 to the right
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self.inv1_inst.place(vector(self.dff_inst.rx(),0))
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# Add INV2 to the right
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self.inv2_inst.place(vector(self.inv1_inst.rx(),0))
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def route_wires(self):
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# Route dff q to inv1 a
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q_pin = self.dff_inst.get_pin("Q")
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a1_pin = self.inv1_inst.get_pin("A")
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mid_x_offset = 0.5*(a1_pin.cx() + q_pin.cx())
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mid1 = vector(mid_x_offset, q_pin.cy())
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mid2 = vector(mid_x_offset, a1_pin.cy())
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self.add_path("metal3", [q_pin.center(), mid1, mid2, a1_pin.center()])
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=q_pin.center())
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=a1_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=a1_pin.center())
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# Route inv1 z to inv2 a
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z1_pin = self.inv1_inst.get_pin("Z")
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a2_pin = self.inv2_inst.get_pin("A")
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mid_x_offset = 0.5*(z1_pin.cx() + a2_pin.cx())
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self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy())
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mid2 = vector(mid_x_offset, a2_pin.cy())
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self.add_path("metal1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()])
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def add_layout_pins(self):
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# Continous vdd rail along with label.
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vdd_pin=self.dff_inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_pin.ll(),
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width=self.width,
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height=vdd_pin.height())
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# Continous gnd rail along with label.
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gnd_pin=self.dff_inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_pin.ll(),
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width=self.width,
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height=vdd_pin.height())
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clk_pin = self.dff_inst.get_pin("clk")
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self.add_layout_pin(text="clk",
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layer=clk_pin.layer,
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offset=clk_pin.ll(),
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width=clk_pin.width(),
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height=clk_pin.height())
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din_pin = self.dff_inst.get_pin("D")
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self.add_layout_pin(text="D",
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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dout_pin = self.inv2_inst.get_pin("Z")
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mid_pos = dout_pin.center() + vector(self.m1_pitch,0)
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q_pos = mid_pos - vector(0,self.m2_pitch)
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self.add_layout_pin_rect_center(text="Q",
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layer="metal2",
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offset=q_pos)
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self.add_path("metal1", [dout_pin.center(), mid_pos, q_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=q_pos)
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qb_pos = self.mid_qb_pos + vector(0,self.m2_pitch)
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self.add_layout_pin_rect_center(text="Qb",
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layer="metal2",
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offset=qb_pos)
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self.add_path("metal1", [self.mid_qb_pos, qb_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=qb_pos)
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def analytical_delay(self, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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dff_delay=self.dff.analytical_delay(slew=slew, load=self.inv1.input_load())
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inv1_delay = self.inv1.analytical_delay(slew=dff_delay.slew, load=self.inv2.input_load())
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inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load)
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return dff_delay + inv1_delay + inv2_delay
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
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#FIXME: Dff changed in a past commit. The parameter need to be updated.
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return parameter["dff_clk_cin"] |