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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00
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b7655eab1030f1a1c641d40c4ab5db571de01deb
OpenRAM/compiler/base
T
History
Matt Guthaus 6990773ea1 Add error check requiring non-zero area pin layouts.
2018-10-29 10:32:42 -07:00
..
contact.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
design.py
Merge branch 'dev' into supply_routing
2018-10-17 09:47:18 -07:00
geometry.py
Odd bug that instances were not properly rotated.
2018-10-24 16:12:27 -07:00
hierarchy_design.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_layout.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
hierarchy_spice.py
Fix print check regression
2018-10-15 13:23:31 -07:00
lef.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
path.py
…
pin_layout.py
Add error check requiring non-zero area pin layouts.
2018-10-29 10:32:42 -07:00
route.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
utils.py
Reduce verbosity of utils
2018-10-26 13:02:31 -07:00
vector.py
Fix Future Warning for real
2018-10-10 15:58:16 -07:00
verilog.py
…
wire.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
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