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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-31 02:06:39 +02:00
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b4ebbdd5df24f29a06eb2f24f9a298e03a51214e
OpenRAM/technology/freepdk45/sp_lib
T
History
jcirimel 35eac54c0d update freepdk bitcell for pex
2020-08-17 17:47:43 -07:00
..
cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
cell_1w_1r.sp
Fix error in cell width. Fix escape warning.
2019-02-24 10:48:54 -08:00
cell_6t.sp
update freepdk bitcell for pex
2020-08-17 17:47:43 -07:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
dummy_cell_1rw_1r.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
dummy_cell_1w_1r.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
dummy_cell_6t.sp
change Qbar to Q_bar in freepdk45 bitcells
2020-08-04 15:21:54 -07:00
replica_cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
replica_cell_1w_1r.sp
Fix mising file
2019-02-24 11:04:56 -08:00
replica_cell_6t.sp
Modify replica cell spice in FreePDK45 to short Qbar to vdd
2018-11-05 11:42:42 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
…
write_driver.sp
…
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