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contact.py
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Update contact well support.
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2020-02-05 18:21:01 +00:00 |
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custom_cell_properties.py
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sense_amp: Allow custom pin names
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2020-02-17 15:20:12 +01:00 |
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delay_data.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
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design.py
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Fix wire width bug in short jogs. PEP8 cleanup.
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2020-04-15 09:48:42 -07:00 |
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errors.py
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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geometry.py
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Add instance center location
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2020-02-28 18:24:09 +00:00 |
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graph_util.py
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Made all cin function relate to farads and all input_load relate to relative units.
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2019-08-08 01:57:04 -07:00 |
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hierarchy_design.py
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Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
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2020-04-03 13:39:54 -07:00 |
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hierarchy_layout.py
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Change to callable DRC rule. Use bottom coordinate for bus offsets.
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2020-04-15 15:29:55 -07:00 |
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hierarchy_spice.py
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Output lvs model instead of spice model
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2020-04-06 14:08:38 -07:00 |
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lef.py
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Added functionality to express polygons in LEF files.
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2019-06-25 09:20:00 -07:00 |
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pin_layout.py
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added purposes to addText(), removed reference to specific tech from gdsMill
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2020-02-19 16:26:52 -08:00 |
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power_data.py
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Move classes to individual file.
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2019-07-16 15:18:04 -07:00 |
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route.py
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Fix space before comment
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2019-06-14 08:43:41 -07:00 |
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utils.py
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s8 gdsless netlist only working up to dff array
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2020-02-09 21:37:09 -08:00 |
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vector.py
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Merge branch 'tech_migration' into dev
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2020-01-25 12:03:56 -08:00 |
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verilog.py
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Feedthru port edits.
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2019-09-27 14:18:49 -07:00 |
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wire.py
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Try both layers for reversed layer stacks.
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2020-04-15 16:49:04 -07:00 |
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wire_path.py
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Fix space before comment
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2019-06-14 08:43:41 -07:00 |
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wire_spice_model.py
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Move classes to individual file.
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2019-07-16 15:18:04 -07:00 |
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