OpenRAM/compiler/characterizer
Hunter Nichols b06aa84824 Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips. 2018-11-23 18:55:15 -08:00
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__init__.py Fix check for missing simulator type in characterizer 2018-10-25 09:08:56 -07:00
charutils.py In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
delay.py In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
functional.py Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips. 2018-11-23 18:55:15 -08:00
lib.py Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
logical_effort.py Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
setup_hold.py Updating ms_flop removal. 2018-09-13 11:40:24 -07:00
simulation.py Convert port index lists to three simple lists. 2018-11-08 12:19:40 -08:00
stimuli.py Add ngspice equivalents of RUNLVL 2018-10-24 10:31:27 -07:00
trim_spice.py Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
worst_case.py Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00