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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 10:39:35 +02:00
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b00fc040a39d126db73eb34ee1b8fa54908a8a2f
OpenRAM/technology/scn4m_subm/mag_lib
T
History
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
..
.magicrc
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
cell_1rw_1r.mag
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
cell_6t.mag
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
convertall.sh
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
dff.mag
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
replica_cell_1rw_1r.mag
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
replica_cell_6t.mag
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sense_amp.mag
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
setup.tcl
Remove old setup.tcl and edit one in tech dir
2018-10-20 15:20:15 -07:00
tri_gate.mag
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.mag
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
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