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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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b00fc040a3
OpenRAM
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technology
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Hunter Nichols
b00fc040a3
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
..
freepdk45
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
scn3me_subm
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
scn4m_subm
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
setup_scripts
Added scn4m_subm.
2018-09-13 12:53:35 -07:00