This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 01:24:39 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
b00fc040a39d126db73eb34ee1b8fa54908a8a2f
OpenRAM
/
technology
T
History
Hunter Nichols
b00fc040a3
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
..
freepdk45
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
scn3me_subm
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
scn4m_subm
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
setup_scripts
Added scn4m_subm.
2018-09-13 12:53:35 -07:00