mrg d4c4658c77 Clean up invalid routing layer error message

2020-11-12 09:43:08 -08:00

..

base

Clean up invalid routing layer error message

2020-11-12 09:43:08 -08:00

bitcells

Fix missing imports in replica bitcells.

2020-11-03 15:24:44 -08:00

characterizer

Fix errors in new run_sim calls and corners

2020-11-09 13:59:46 -08:00

custom

Use custom cells when needed.

2020-11-03 11:58:25 -08:00

datasheet

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

drc

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

example_configs

Create single port memory config examples.

2020-11-03 14:42:56 -08:00

gdsMill

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

modules

Use OPTS.bitcell everywhere

2020-11-05 16:55:08 -08:00

pgates

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Adjust openram options.

2020-11-05 13:12:26 -08:00

sram

Add 200 cycles. Can be commented out or run for shorter.

2020-11-09 15:20:36 -08:00

tests

Merge branch 'drclvs' into dev

2020-11-09 14:36:36 -08:00

verify

Temp comment Magic GDS filter code.

2020-11-10 13:37:18 -08:00

debug.py

Cleanup imports

2020-11-05 14:32:08 -08:00

gen_stimulus.py

…

globals.py

Fix errors in new run_sim calls and corners

2020-11-09 13:59:46 -08:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

options.py

Adjust openram options.

2020-11-05 13:12:26 -08:00

run_profile.sh

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sram_factory.py

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

view_profile.py

…