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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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9907daaffa8557af0edc324623d5f8358c3dc172
OpenRAM/compiler/base
T
History
mrg 9907daaffa Min area only for multiple layers
2020-03-26 13:05:02 -07:00
..
contact.py
Update contact well support.
2020-02-05 18:21:01 +00:00
custom_cell_properties.py
sense_amp: Allow custom pin names
2020-02-17 15:20:12 +01:00
delay_data.py
Remove some flake8 errors/warnings.
2019-10-02 23:26:02 +00:00
design.py
Add general well_extend_active DRC in design class.
2020-02-05 18:22:22 +00:00
geometry.py
Add instance center location
2020-02-28 18:24:09 +00:00
graph_util.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
hierarchy_design.py
Allow gds to be written with supplies off. Fix extraction bug with new options.
2019-09-03 11:23:35 -07:00
hierarchy_layout.py
Min area only for multiple layers
2020-03-26 13:05:02 -07:00
hierarchy_spice.py
Share nominal temperature and voltage. Nominal instead of typical.
2019-09-04 16:53:58 -07:00
lef.py
…
pin_layout.py
added purposes to addText(), removed reference to specific tech from gdsMill
2020-02-19 16:26:52 -08:00
power_data.py
…
route.py
…
utils.py
s8 gdsless netlist only working up to dff array
2020-02-09 21:37:09 -08:00
vector.py
Merge branch 'tech_migration' into dev
2020-01-25 12:03:56 -08:00
verilog.py
Feedthru port edits.
2019-09-27 14:18:49 -07:00
wire_path.py
…
wire_spice_model.py
…
wire.py
…
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