mrg 9beb0f4ece Add separate well design rules. ...

Needed to fix various pgates with wells.
Did some cleanup of these gates as well.

2020-01-23 19:43:41 +00:00

..

gds_lib

Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver.

2019-08-08 15:49:23 -07:00

mag_lib

Fix magicrc for multiple openram tech paths

2019-10-24 13:17:33 -07:00

models

Adjusted vth0 of FF and SS models in scn4m from nominal.

2019-10-07 15:26:20 -07:00

sp_lib

Remove unnecessary footer in write driver

2019-08-01 08:59:41 -07:00

sue_lib

Added scn4m_subm.

2018-09-13 12:53:35 -07:00

tech

Add separate well design rules.

2020-01-23 19:43:41 +00:00

tf

Add Metal3/Via3/Metal4 on right gds layers

2019-09-03 15:28:20 -07:00

__init__.py

Move DRC/LVS/PEX tools to tech file.

2019-11-29 12:01:33 -08:00