OpenRAM/compiler/modules
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only
mode is enabled.
2018-08-27 16:42:48 -07:00
..
bank.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
bank_select.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
bitcell.py Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly. 2018-08-26 14:37:17 -07:00
bitcell_array.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
control_logic.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
delay_chain.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
dff.py Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
dff_array.py Add place_inst routine. 2018-08-27 10:42:40 -07:00
dff_buf.py Limit sizes for dff_buf too. Add comments about restriction. 2018-07-27 08:17:50 -07:00
dff_buf_array.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
dff_inv.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
dff_inv_array.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
hierarchical_decoder.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
hierarchical_predecode.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
hierarchical_predecode2x4.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
hierarchical_predecode3x8.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
ms_flop.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
ms_flop_array.py Separate netlist/layout for flop and precharge array. 2018-08-27 10:54:21 -07:00
precharge_array.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
replica_bitcell.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
replica_bitline.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
sense_amp.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
sense_amp_array.py All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
single_level_column_mux_array.py All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
tri_gate.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
tri_gate_array.py All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
wordline_driver.py Converted all modules to not run create_layout when netlist_only 2018-08-27 16:42:48 -07:00
write_driver.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
write_driver_array.py All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00