mirror of https://github.com/VLSIDA/OpenRAM.git
527 lines
21 KiB
Python
527 lines
21 KiB
Python
import debug
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import design
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from tech import drc
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from pinv import pinv
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import contact
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from bitcell_array import bitcell_array
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from ptx import ptx
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from vector import vector
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from globals import OPTS
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class replica_bitline(design.design):
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"""
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Generate a module that simulates the delay of control logic
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and bit line charging. Stages is the depth of the delay
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line and rows is the height of the replica bit loads.
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"""
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def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"):
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design.design.__init__(self, name)
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from importlib import reload
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g = reload(__import__(OPTS.delay_chain))
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self.mod_delay_chain = getattr(g, OPTS.delay_chain)
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g = reload(__import__(OPTS.replica_bitcell))
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self.mod_replica_bitcell = getattr(g, OPTS.replica_bitcell)
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self.bitcell_loads = bitcell_loads
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self.delay_stages = delay_stages
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self.delay_fanout = delay_fanout
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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for pin in ["en", "out", "vdd", "gnd"]:
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self.add_pin(pin)
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self.add_modules()
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self.create_modules()
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def create_layout(self):
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self.calculate_module_offsets()
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self.place_modules()
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self.route()
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self.offset_all_coordinates()
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self.add_layout_pins()
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#self.add_lvs_correspondence_points()
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# Extra pitch on top and right
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self.width = self.rbl_inst.rx() - self.dc_inst.lx() + self.m2_pitch
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self.height = max(self.rbl_inst.uy(), self.dc_inst.uy()) + self.m3_pitch
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self.DRC_LVS()
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def calculate_module_offsets(self):
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""" Calculate all the module offsets """
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# These aren't for instantiating, but we use them to get the dimensions
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self.poly_contact_offset = vector(0.5*contact.poly.width,0.5*contact.poly.height)
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# Quadrant 1: Replica bitline and such are not rotated, but they must be placed far enough
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# away from the delay chain/inverter with space for three M2 tracks
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self.bitcell_offset = vector(0,self.replica_bitcell.height)
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self.rbl_offset = self.bitcell_offset
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# Gap between the delay chain and RBL
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gap_width = 2*self.m2_pitch
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# Quadrant 4: with some space below it and tracks on the right for vdd/gnd
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self.delay_chain_offset = vector(-self.delay_chain.width-gap_width,self.replica_bitcell.height)
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# Will be flipped vertically below the delay chain
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# Align it with the inverters in the delay chain to simplify supply connections
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self.rbl_inv_offset = self.delay_chain_offset + vector(2*self.inv.width, 0)
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# Placed next to the replica bitcell
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self.access_tx_offset = vector(-gap_width-self.access_tx.width-self.inv.width, 0.5*self.inv.height)
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def add_modules(self):
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""" Add the modules for later usage """
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self.bitcell = self.replica_bitcell = self.mod_replica_bitcell()
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self.add_mod(self.bitcell)
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# This is the replica bitline load column that is the height of our array
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self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads)
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self.add_mod(self.rbl)
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# FIXME: The FO and depth of this should be tuned
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self.delay_chain = self.mod_delay_chain([self.delay_fanout]*self.delay_stages)
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self.add_mod(self.delay_chain)
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self.inv = pinv()
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self.add_mod(self.inv)
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self.access_tx = ptx(tx_type="pmos")
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self.add_mod(self.access_tx)
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def create_modules(self):
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""" Create all of the module instances in the logical netlist """
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# This is the threshold detect inverter on the output of the RBL
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self.rbl_inv_inst=self.add_inst(name="rbl_inv",
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mod=self.inv)
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self.connect_inst(["bl[0]", "out", "vdd", "gnd"])
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self.tx_inst=self.add_inst(name="rbl_access_tx",
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mod=self.access_tx)
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# D, G, S, B
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self.connect_inst(["vdd", "delayed_en", "bl[0]", "vdd"])
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# add the well and poly contact
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self.dc_inst=self.add_inst(name="delay_chain",
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mod=self.delay_chain)
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self.connect_inst(["en", "delayed_en", "vdd", "gnd"])
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self.rbc_inst=self.add_inst(name="bitcell",
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mod=self.replica_bitcell)
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self.connect_inst(["bl[0]", "br[0]", "delayed_en", "vdd", "gnd"])
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self.rbl_inst=self.add_inst(name="load",
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mod=self.rbl)
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self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.bitcell_loads + ["vdd", "gnd"])
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def place_modules(self):
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""" Add all of the module instances in the logical netlist """
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# This is the threshold detect inverter on the output of the RBL
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self.place_inst(name="rbl_inv",
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offset=self.rbl_inv_offset,
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rotate=180)
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self.place_inst(name="rbl_access_tx",
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offset=self.access_tx_offset)
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self.place_inst(name="delay_chain",
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offset=self.delay_chain_offset)
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self.place_inst(name="bitcell",
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offset=self.bitcell_offset,
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mirror="MX")
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self.place_inst(name="load",
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offset=self.rbl_offset)
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def route(self):
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""" Connect all the signals together """
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self.route_supplies()
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self.route_wl()
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self.route_access_tx()
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def route_wl(self):
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""" Connect the RBL word lines to gnd """
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# Connect the WL and gnd pins directly to the center and right gnd rails
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for row in range(self.bitcell_loads):
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wl = "wl[{}]".format(row)
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pin = self.rbl_inst.get_pin(wl)
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# Route the connection to the right so that it doesn't interfere
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# with the cells
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pin_right = pin.rc()
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pin_extension = pin_right + vector(self.m1_pitch,0)
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if pin.layer != "metal1":
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continue
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self.add_path("metal1", [pin_right, pin_extension])
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self.add_power_pin("gnd", pin_extension)
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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# These are the instances that every bank has
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top_instances = [self.rbl_inst,
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self.dc_inst]
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for inst in top_instances:
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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# Route the inverter supply pin from M1
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# Only vdd is needed because gnd shares a rail with the delay chain
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pin = self.rbl_inv_inst.get_pin("vdd")
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self.add_power_pin("vdd", pin.lc())
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# Replica bitcell needs to be routed up to M3
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pin=self.rbc_inst.get_pin("vdd")
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# Don't rotate this via to vit in FreePDK45
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self.add_power_pin("vdd", pin.center(), False)
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for pin in self.rbc_inst.get_pins("gnd"):
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self.add_power_pin("gnd", pin.center())
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def route_access_tx(self):
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# GATE ROUTE
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# 1. Add the poly contact and nwell enclosure
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# Determines the y-coordinate of where to place the gate input poly pin
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# (middle in between the pmos and nmos)
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poly_pin = self.tx_inst.get_pin("G")
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poly_offset = poly_pin.uc()
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# This centers the contact above the poly by one pitch
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contact_offset = poly_offset + vector(0,self.m2_pitch)
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self.add_contact_center(layers=("poly", "contact", "metal1"),
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offset=contact_offset)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=contact_offset)
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self.add_segment_center(layer="poly",
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start=poly_offset,
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end=contact_offset)
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nwell_offset = self.rbl_inv_offset + vector(-self.inv.height,self.inv.width)
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# self.add_rect(layer="nwell",
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# offset=nwell_offset,
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# width=0.5*self.inv.height,
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# height=self.delay_chain_offset.y-nwell_offset.y)
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# 2. Route delay chain output to access tx gate
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delay_en_offset = self.dc_inst.get_pin("out").bc()
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self.add_path("metal2", [delay_en_offset,contact_offset])
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# 3. Route the contact of previous route to the bitcell WL
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# route bend of previous net to bitcell WL
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wl_offset = self.rbc_inst.get_pin("WL").lc()
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xmid_point= 0.5*(wl_offset.x+contact_offset.x)
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wl_mid1 = vector(xmid_point,contact_offset.y)
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wl_mid2 = vector(xmid_point,wl_offset.y)
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self.add_path("metal1", [contact_offset, wl_mid1, wl_mid2, wl_offset])
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# DRAIN ROUTE
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# Route the drain to the vdd rail
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drain_offset = self.tx_inst.get_pin("D").center()
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self.add_power_pin("vdd", drain_offset)
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# SOURCE ROUTE
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# Route the drain to the RBL inverter input
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source_offset = self.tx_inst.get_pin("S").center()
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inv_A_offset = self.rbl_inv_inst.get_pin("A").center()
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self.add_path("metal1",[source_offset, inv_A_offset])
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# Route the connection of the source route to the RBL bitline (left)
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# Via will go halfway down from the bitcell
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bl_offset = self.rbc_inst.get_pin("BL").bc()
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# Route down a pitch so we can use M2 routing
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bl_down_offset = bl_offset - vector(0, self.m2_pitch)
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self.add_path("metal2",[source_offset, bl_down_offset, bl_offset])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=source_offset)
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# BODY ROUTE
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# Connect it to the inverter well
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nwell_offset = self.rbl_inv_inst.lr()
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ur_offset = self.tx_inst.ur()
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self.add_rect(layer="nwell",
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offset=nwell_offset,
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width=ur_offset.x-nwell_offset.x,
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height=ur_offset.y-nwell_offset.y)
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def route_vdd(self):
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""" Route all signals connected to vdd """
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self.copy_layout_pin(self.dc_inst,"vdd")
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self.copy_layout_pin(self.rbc_inst,"vdd")
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# Connect the WL and vdd pins directly to the center and right vdd rails
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# Connect RBL vdd pins to center and right rails
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rbl_vdd_pins = self.rbl_inst.get_pins("vdd")
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for pin in rbl_vdd_pins:
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if pin.layer != "metal1":
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continue
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start = vector(self.center_vdd_pin.cx(),pin.cy())
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end = vector(self.right_vdd_pin.cx(),pin.cy())
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self.add_layout_pin_segment_center(text="vdd",
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layer="metal1",
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start=start,
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end=end)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=start,
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rotate=90)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end,
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rotate=90)
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# Add via for the inverter
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pin = self.rbl_inv_inst.get_pin("vdd")
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start = vector(self.left_vdd_pin.cx(),pin.cy())
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end = vector(self.center_vdd_pin.cx(),pin.cy())
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self.add_segment_center(layer="metal1",
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start=start,
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end=end)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=start,
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rotate=90)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end,
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rotate=90)
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# Add via for the RBC
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pin = self.rbc_inst.get_pin("vdd")
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start = pin.lc()
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end = vector(self.right_vdd_pin.cx(),pin.cy())
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self.add_segment_center(layer="metal1",
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start=start,
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end=end)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end,
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rotate=90)
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# Create the RBL rails too
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rbl_pins = self.rbl_inst.get_pins("vdd")
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for pin in rbl_pins:
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if pin.layer != "metal1":
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continue
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# If above the delay line, route the full width
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left = vector(self.left_vdd_pin.cx(),pin.cy())
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center = vector(self.center_vdd_pin.cx(),pin.cy())
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if pin.cy() > self.dc_inst.uy() + self.m1_pitch:
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start = left
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=left,
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rotate=90)
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else:
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start = center
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end = vector(self.right_vdd_pin.cx()+0.5*self.m1_width,pin.cy())
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self.add_layout_pin_segment_center(text="vdd",
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layer="metal1",
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start=start,
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end=end)
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def route_gnd(self):
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""" Route all signals connected to gnd """
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# Route the gnd lines from left to right
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# Add via for the delay chain
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left_gnd_start = self.dc_inst.ll().scale(1,0) - vector(2*self.m2_pitch,0)
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left_gnd_end = vector(left_gnd_start.x, self.rbl_inst.uy()+self.m2_pitch)
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self.left_gnd_pin=self.add_segment_center(layer="metal2",
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start=left_gnd_start,
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end=left_gnd_end)
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# Gnd line to the left of the replica bitline
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center_gnd_start = self.rbc_inst.ll().scale(1,0) - vector(2*self.m2_pitch,0)
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center_gnd_end = vector(center_gnd_start.x, self.rbl_inst.uy()+self.m2_pitch)
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self.center_gnd_pin=self.add_segment_center(layer="metal2",
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start=center_gnd_start,
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end=center_gnd_end)
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# Gnd line to the right of the replica bitline
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right_gnd_start = self.rbc_inst.lr().scale(1,0) + vector(self.m2_pitch,0)
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right_gnd_end = vector(right_gnd_start.x, self.rbl_inst.uy()+self.m2_pitch)
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self.right_gnd_pin=self.add_segment_center(layer="metal2",
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start=right_gnd_start,
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end=right_gnd_end)
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# Connect the WL and gnd pins directly to the center and right gnd rails
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for row in range(self.bitcell_loads):
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wl = "wl[{}]".format(row)
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pin = self.rbl_inst.get_pin(wl)
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if pin.layer != "metal1":
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continue
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# If above the delay line, route the full width
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left = vector(self.left_gnd_pin.cx(),pin.cy())
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center = vector(self.center_gnd_pin.cx(),pin.cy())
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if pin.cy() > self.dc_inst.uy() + self.m1_pitch:
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start = left
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else:
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start = center
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end = vector(self.right_gnd_pin.cx(),pin.cy())
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self.add_layout_pin_segment_center(text="gnd",
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layer="metal1",
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start=start,
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end=end)
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if start == left:
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=left,
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rotate=90)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=center,
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rotate=90)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end,
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rotate=90)
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rbl_gnd_pins = self.rbl_inst.get_pins("gnd")
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# Add L shapes to each vertical gnd rail
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for pin in rbl_gnd_pins:
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if pin.layer != "metal1":
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continue
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# If above the delay line, route the full width
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left = vector(self.left_gnd_pin.cx(),pin.cy())
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center = vector(self.center_gnd_pin.cx(),pin.cy())
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if pin.cy() > self.dc_inst.uy() + self.m1_pitch:
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start = left
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else:
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start = center
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end = vector(self.right_gnd_pin.cx(),pin.cy())
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self.add_segment_center(layer="metal1",
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start=start,
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end=end)
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if start == left:
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=left,
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rotate=90)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=center,
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rotate=90)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end,
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rotate=90)
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# Connect the gnd pins of the delay chain to the left rails
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dc_gnd_pins = self.dc_inst.get_pins("gnd")
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for pin in dc_gnd_pins:
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if pin.layer != "metal1":
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continue
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start = vector(self.left_gnd_pin.cx(),pin.cy())
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# Note, we don't connect to the center rails because of
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# via conflicts with the RBL
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#end = vector(self.center_gnd_pin.cx(),pin.cy())
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end = pin.rc()
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self.add_segment_center(layer="metal1",
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start=start,
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end=end)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=start,
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rotate=90)
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# self.add_via_center(layers=("metal1", "via1", "metal2"),
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# offset=end,
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#rotate=90)
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# Add via for the inverter
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# pin = self.rbl_inv_inst.get_pin("gnd")
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# start = vector(self.left_gnd_pin.cx(),pin.cy())
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# end = vector(self.center_gnd_pin.cx(),pin.cy())
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# self.add_segment_center(layer="metal1",
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# start=start,
|
|
# end=end)
|
|
# self.add_via_center(layers=("metal1", "via1", "metal2"),
|
|
# offset=start,
|
|
#rotate=90)
|
|
# self.add_via_center(layers=("metal1", "via1", "metal2"),
|
|
# offset=end,
|
|
#rotate=90)
|
|
|
|
|
|
|
|
# Create RBL rails too
|
|
rbl_pins = self.rbl_inst.get_pins("gnd")
|
|
for pin in rbl_pins:
|
|
if pin.layer != "metal2":
|
|
continue
|
|
start = vector(pin.cx(),self.right_gnd_pin.by())
|
|
end = vector(pin.cx(),self.right_gnd_pin.uy())
|
|
self.add_layout_pin_segment_center(text="gnd",
|
|
layer="metal2",
|
|
start=start,
|
|
end=end)
|
|
|
|
|
|
|
|
def add_layout_pins(self):
|
|
""" Route the input and output signal """
|
|
en_offset = self.dc_inst.get_pin("in").bc()
|
|
self.add_layout_pin_segment_center(text="en",
|
|
layer="metal2",
|
|
start=en_offset,
|
|
end=en_offset.scale(1,0))
|
|
|
|
out_offset = self.rbl_inv_inst.get_pin("Z").center()
|
|
self.add_layout_pin_segment_center(text="out",
|
|
layer="metal2",
|
|
start=out_offset,
|
|
end=out_offset.scale(1,0))
|
|
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
|
offset=out_offset)
|
|
|
|
def add_lvs_correspondence_points(self):
|
|
""" This adds some points for easier debugging if LVS goes wrong.
|
|
These should probably be turned off by default though, since extraction
|
|
will show these as ports in the extracted netlist.
|
|
"""
|
|
|
|
pin = self.rbl_inv_inst.get_pin("A")
|
|
self.add_label_pin(text="bl[0]",
|
|
layer=pin.layer,
|
|
offset=pin.ll(),
|
|
height=pin.height(),
|
|
width=pin.width())
|
|
|
|
pin = self.dc_inst.get_pin("out")
|
|
self.add_label_pin(text="delayed_en",
|
|
layer=pin.layer,
|
|
offset=pin.ll(),
|
|
height=pin.height(),
|
|
width=pin.width())
|
|
|