Matt Guthaus 85595b0f6f Update format of delay test output during an error to directly ...

copy into unit test. Factor function into testutils.py for comparison.

2018-07-26 16:05:24 -07:00

..

base

Remove print statement

2018-07-25 15:51:48 -07:00

characterizer

Convert bitline index to integer in trim_spice

2018-07-26 14:29:44 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Make pinvbuf have unique names for GDS compliance.

2018-07-26 11:40:40 -07:00

pgates

Make pinvbuf have unique names for GDS compliance.

2018-07-26 11:40:40 -07:00

router

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tests

Update format of delay test output during an error to directly

2018-07-26 16:05:24 -07:00

verify

Add temporary options to LVS to allow name merging

2018-07-18 15:10:29 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Fix num words in example.

2018-02-23 12:17:43 -08:00

example_config_scn3me_subm.py

Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.

2018-02-12 11:22:47 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Only print LVS/DRC stats when it is enabled

2018-07-25 13:44:34 -07:00

Makefile

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openram.py

Improve openram output. Fix save output function name.

2018-07-12 10:35:38 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch.

2018-07-25 15:50:49 -07:00

sram_2bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_4bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_base.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram.py

Add verilog_write to sram wrapper for verilog unit test

2018-07-19 10:05:30 -07:00