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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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7ad2d54a69e008aa7d65acce25618fdd5131cc15
OpenRAM/compiler/pgates
T
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mrg 1a2e0046b1 Add contact to gate spacing for precharge
2020-06-11 11:54:34 -07:00
..
pand2.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pand3.py
Vertical gates need both well contacts.
2020-05-13 16:54:35 -07:00
pbuf.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pdriver.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pgate.py
Merge branch 'tech_migration' into dev
2020-06-10 17:09:05 -07:00
pinv_dec.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pinv.py
Check min size inverter.
2020-05-13 16:54:26 -07:00
pinvbuf.py
Fix pinvbuf layers
2020-06-09 17:16:35 -07:00
pnand2.py
Incrase space for pnand gates
2020-06-09 16:34:15 -07:00
pnand3.py
More exact input spacing in pnand3
2020-06-10 16:19:24 -07:00
pnor2.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
precharge.py
Add contact to gate spacing for precharge
2020-06-11 11:54:34 -07:00
ptristate_inv.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptx.py
Save LVS model with no u too for Calibre
2020-06-11 11:53:34 -07:00
pwrite_driver.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
single_level_column_mux.py
Fix the bitline spacing in the column mux to a constant.
2020-06-03 15:47:03 -07:00
wordline_driver.py
Hard cells can accept height parameter too.
2020-06-01 16:46:00 -07:00
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