mrg 2ccf3aea3b Set channel route height and width (of routes, not pins)		2020-07-20 13:25:47 -07:00
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channel_route.py	Set channel route height and width (of routes, not pins)	2020-07-20 13:25:47 -07:00
contact.py	Add npc enclosure to poly contacts	2020-06-11 11:53:59 -07:00
custom_cell_properties.py	sense_amp: Allow custom pin names	2020-02-17 15:20:12 +01:00
delay_data.py	Remove some flake8 errors/warnings.	2019-10-02 23:26:02 +00:00
design.py	Separate active and poly contact to gate rule	2020-06-24 09:17:39 -07:00
errors.py	Add exception errors file	2020-04-08 16:55:45 -07:00
geometry.py	Thin-cell decoder changes.	2020-05-29 10:36:07 -07:00
graph_util.py	…
hierarchy_design.py	Default drc and lvs errors is skipped.	2020-07-13 14:08:00 -07:00
hierarchy_layout.py	Add parent to channel route for dumpign debug gds.	2020-07-20 12:03:25 -07:00
hierarchy_spice.py	PEP8 formatting	2020-06-23 15:39:26 -07:00
lef.py	…
pin_layout.py	Only do reverse lookup on valid interconnect layers since layer numbers can be shared.	2020-06-29 14:42:24 -07:00
power_data.py	…
route.py	…
utils.py	s8 gdsless netlist only working up to dff array	2020-02-09 21:37:09 -08:00
vector.py	Merge branch 'tech_migration' into dev	2020-01-25 12:03:56 -08:00
verilog.py	…
wire.py	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
wire_path.py	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
wire_spice_model.py	…