OpenRAM/compiler/base
Joey Kunzler 7920b0cef9 m3 min area rounding fix 2020-04-17 12:36:48 -07:00
..
contact.py Update contact well support. 2020-02-05 18:21:01 +00:00
custom_cell_properties.py sense_amp: Allow custom pin names 2020-02-17 15:20:12 +01:00
delay_data.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
design.py Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
errors.py Add exception errors file 2020-04-08 16:55:45 -07:00
geometry.py Add instance center location 2020-02-28 18:24:09 +00:00
graph_util.py Made all cin function relate to farads and all input_load relate to relative units. 2019-08-08 01:57:04 -07:00
hierarchy_design.py Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation) 2020-04-03 13:39:54 -07:00
hierarchy_layout.py m3 min area rounding fix 2020-04-17 12:36:48 -07:00
hierarchy_spice.py Output lvs model instead of spice model 2020-04-06 14:08:38 -07:00
lef.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
pin_layout.py added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Fix space before comment 2019-06-14 08:43:41 -07:00
utils.py s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
vector.py Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
verilog.py Feedthru port edits. 2019-09-27 14:18:49 -07:00
wire.py Don't widen too short wires either 2020-04-16 11:02:54 -07:00
wire_path.py Fix space before comment 2019-06-14 08:43:41 -07:00
wire_spice_model.py Move classes to individual file. 2019-07-16 15:18:04 -07:00