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bank.py
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Must channel rout the column mux bits since they could overlap
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2018-11-16 16:21:31 -08:00 |
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bank_select.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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bitcell_array.py
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Uniquify bitcell array
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2018-11-16 12:52:22 -08:00 |
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control_logic.py
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Two m1 pitches at top of control logic
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2018-11-18 09:30:27 -08:00 |
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delay_chain.py
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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dff.py
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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dff_array.py
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Merge branch 'multiport' into supply_routing
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2018-10-11 09:56:38 -07:00 |
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dff_buf.py
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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dff_buf_array.py
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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dff_inv.py
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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dff_inv_array.py
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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hierarchical_decoder.py
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Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.
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2018-10-20 12:54:12 -07:00 |
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hierarchical_predecode.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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hierarchical_predecode2x4.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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hierarchical_predecode3x8.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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multibank.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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precharge_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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replica_bitline.py
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Uniquify bitcell array
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2018-11-16 12:52:22 -08:00 |
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sense_amp.py
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Document why sense amp is 8x isolation transistor
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2018-11-07 16:09:50 -08:00 |
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sense_amp_array.py
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Fixed spacing in golden lib files. Added column mux into analytical model.
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2018-10-24 00:16:26 -07:00 |
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single_level_column_mux_array.py
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Change default col mux size to 2. Add some comments.
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2018-11-07 15:43:08 -08:00 |
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tri_gate.py
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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tri_gate_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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wordline_driver.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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write_driver.py
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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write_driver_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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