mirror of https://github.com/VLSIDA/OpenRAM.git
271 lines
11 KiB
Python
271 lines
11 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import bitcell_base_array
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from globals import OPTS
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from sram_factory import factory
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from vector import vector
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import debug
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from numpy import cumsum
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class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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"""
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Creates a global bitcell array.
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Rows is an integer number for all local arrays.
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Cols is a list of the array widths.
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"""
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def __init__(self, rows, cols, name=""):
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# The total of all columns will be the number of columns
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super().__init__(name=name, rows=rows, cols=sum(cols), column_offset=0)
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self.column_sizes = cols
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self.col_offsets = [0] + list(cumsum(cols)[:-1])
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debug.check(len(self.all_ports)<=2, "Only support dual port or less in global bitcell array.")
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self.rbl = [1, 1 if len(self.all_ports)>1 else 0]
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place()
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self.route()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.local_mods = []
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# Special case of a single local array
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# so it should contain the left and possibly right RBL
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if len(self.column_sizes) == 1:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=self.column_sizes[0],
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rbl=self.rbl,
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left_rbl=[0],
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right_rbl=[1] if len(self.all_ports) > 1 else [])
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self.add_mod(la)
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self.local_mods.append(la)
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return
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for i, cols in enumerate(self.column_sizes):
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# Always add the left RBLs to the first subarray
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if i == 0:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl,
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left_rbl=[0])
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# Add the right RBL to the last subarray
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elif i == len(self.column_sizes) - 1 and len(self.all_ports) > 1:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl,
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right_rbl=[1])
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# Middle subarrays do not have any RBLs
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else:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl)
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self.add_mod(la)
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self.local_mods.append(la)
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def add_pins(self):
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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self.bitline_names = [[] for x in self.all_ports]
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self.rbl_bitline_names = [[] for x in self.all_ports]
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for port in self.all_ports:
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self.rbl_bitline_names[0].append("rbl_bl_{}_0".format(port))
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for port in self.all_ports:
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self.rbl_bitline_names[0].append("rbl_br_{}_0".format(port))
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for col in range(self.column_size):
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for port in self.all_ports:
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self.bitline_names[port].append("bl_{0}_{1}".format(port, col))
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for port in self.all_ports:
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self.bitline_names[port].append("br_{0}_{1}".format(port, col))
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if len(self.all_ports) > 1:
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for port in self.all_ports:
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self.rbl_bitline_names[1].append("rbl_bl_{}_1".format(port))
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for port in self.all_ports:
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self.rbl_bitline_names[1].append("rbl_br_{}_1".format(port))
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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# Make a flat list too
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self.all_rbl_bitline_names = [x for sl in zip(*self.rbl_bitline_names) for x in sl]
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self.add_pin_list(self.rbl_bitline_names[0], "INOUT")
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self.add_pin_list(self.all_bitline_names, "INOUT")
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if len(self.all_ports) > 1:
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self.add_pin_list(self.rbl_bitline_names[1], "INOUT")
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def add_wordline_pins(self):
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self.rbl_wordline_names = [[] for x in self.all_ports]
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self.wordline_names = [[] for x in self.all_ports]
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for bit in self.all_ports:
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for port in self.all_ports:
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in zip(*self.rbl_wordline_names) for x in sl]
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# Regular WLs
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for row in range(self.row_size):
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for port in self.all_ports:
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.local_insts = []
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for col, mod in zip(self.col_offsets, self.local_mods):
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name = "la_{0}".format(col)
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self.local_insts.append(self.add_inst(name=name,
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mod=mod))
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temp = []
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if col == 0:
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temp.extend(self.get_rbl_bitline_names(0))
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port_inouts = [x for x in mod.get_inouts() if x.startswith("bl") or x.startswith("br")]
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for pin_name in port_inouts:
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# Offset of the last underscore that defines the bit number
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bit_index = pin_name.rindex('_')
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# col is the bit offset of the local array,
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# while col_value is the offset within this array
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col_value = int(pin_name[bit_index + 1:])
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# Name of signal without the bit
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base_name = pin_name[:bit_index]
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# Strip the bit and add the new one
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new_name = "{0}_{1}".format(base_name, col + col_value)
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temp.append(new_name)
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if len(self.all_ports) > 1 and mod == self.local_mods[-1]:
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temp.extend(self.get_rbl_bitline_names(1))
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for port in self.all_ports:
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port_inputs = [x for x in mod.get_inputs() if "wl_{}".format(port) in x]
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temp.extend(port_inputs)
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def place(self):
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offset = vector(0, 0)
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for inst in self.local_insts:
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inst.place(offset)
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offset = inst.rx() + 3 * self.m3_pitch
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self.height = self.local_mods[0].height
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self.width = self.local_insts[-1].rx()
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def route(self):
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pass
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def add_layout_pins(self):
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# Regular bitlines
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for col, inst in zip(self.col_offsets, self.local_insts):
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for port in self.all_ports:
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port_inouts = [x for x in inst.mod.get_inouts() if x.startswith("bl_{}".format(port)) or x.startswith("br_{}".format(port))]
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for pin_name in port_inouts:
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# Offset of the last underscore that defines the bit number
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bit_index = pin_name.rindex('_')
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# col is the bit offset of the local array,
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# while col_value is the offset within this array
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col_value = int(pin_name[bit_index + 1:])
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# Name of signal without the bit
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base_name = pin_name[:bit_index]
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# Strip the bit and add the new one
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new_name = "{0}_{1}".format(base_name, col + col_value)
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self.copy_layout_pin(inst, pin_name, new_name)
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for wl_name in self.local_mods[0].get_inputs():
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left_pin = self.local_insts[0].get_pin(wl_name)
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right_pin = self.local_insts[-1].get_pin(wl_name)
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self.add_layout_pin_segment_center(text=wl_name,
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layer=left_pin.layer,
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start=left_pin.lc(),
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end=right_pin.rc())
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# Replica bitlines
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self.copy_layout_pin(self.local_insts[0], "rbl_bl_0_0")
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self.copy_layout_pin(self.local_insts[0], "rbl_br_0_0")
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if len(self.all_ports) > 1:
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self.copy_layout_pin(self.local_insts[0], "rbl_bl_1_0")
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self.copy_layout_pin(self.local_insts[0], "rbl_br_1_0")
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_0_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_0_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_bl_1_1")
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self.copy_layout_pin(self.local_insts[-1], "rbl_br_1_1")
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for inst in self.insts:
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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def get_main_array_top(self):
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return self.local_insts[0].offset.y + self.local_mods[0].get_main_array_top()
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def get_main_array_bottom(self):
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return self.local_insts[0].offset.y + self.local_mods[0].get_main_array_bottom()
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def get_main_array_left(self):
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return self.local_insts[0].offset.x + self.local_mods[0].get_main_array_left()
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def get_main_array_right(self):
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return self.local_insts[-1].offset.x + self.local_mods[-1].get_main_array_right()
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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offsets = []
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for inst in self.local_insts:
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offsets.extend(inst.lx() + x for x in inst.mod.get_column_offsets())
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return offsets
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