luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
6a8a76dd23a422eb23de332e3b8c9f728dc90e91
OpenRAM/compiler/modules
T
History
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl
2022-12-14 08:13:08 -08:00
..
__init__.py
Move sram and sram_config to openram namespace
2022-12-02 15:28:06 -08:00
and2_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
and3_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
and4_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
bank.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
bitcell_1port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
bitcell_2port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
bitcell_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
bitcell_base_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
bitcell_base.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
capped_bitcell_array.py
route unused wordlines (still failing lvs)
2022-12-14 08:12:55 -08:00
col_cap_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
col_cap_bitcell_1port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
col_cap_bitcell_2port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
column_decoder.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
column_mux_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
column_mux.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
control_logic_base.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
control_logic.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
delay_chain.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dff_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dff_buf_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dff_buf.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dff_inv_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dff_inv.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dff.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dummy_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
dummy_bitcell_1port.py
Add empty build_graph() for dummy bitcells
2022-12-02 12:14:40 -08:00
dummy_bitcell_2port.py
Add empty build_graph() for dummy bitcells
2022-12-02 12:14:40 -08:00
dummy_pbitcell.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
global_bitcell_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
hierarchical_decoder.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
hierarchical_predecode2x4.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
hierarchical_predecode3x8.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
hierarchical_predecode4x16.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
hierarchical_predecode.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
internal_base.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
inv_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
local_bitcell_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
multibank.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
nand2_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
nand3_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
nand4_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
orig_bitcell_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pand2.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pand3.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pand4.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pbitcell.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pbuf_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pbuf.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pdriver.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pgate.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pinv_dec.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pinv.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pinvbuf.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pnand2.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pnand3.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pnand4.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pnor2.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
port_address.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
port_data.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
precharge_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
precharge.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
ptristate_inv.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
ptx.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
pwrite_driver.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
replica_bitcell_1port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
replica_bitcell_2port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
replica_bitcell_array.py
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl
2022-12-14 08:13:08 -08:00
replica_column.py
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl
2022-12-14 08:13:08 -08:00
replica_pbitcell.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
row_cap_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
row_cap_bitcell_1port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
row_cap_bitcell_2port.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
sense_amp_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
sense_amp.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
sram_1bank.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
sram_multibank_template.v
Shrunk address register in multibank verilog
2022-07-28 15:03:41 -07:00
sram_multibank.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
template.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
tri_gate_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
tri_gate.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
wordline_buffer_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
wordline_driver_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
wordline_driver.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
write_driver_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
write_driver.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
write_mask_and_array.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00