OpenRAM

characterizer

Fix broken print statements

2018-02-07 17:39:42 -08:00

gdsMill

Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.

2017-12-12 15:50:45 -08:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

Update unit test results

2018-02-07 18:48:22 -08:00

verify

Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.

2018-02-05 16:02:57 -08:00

bank.py

Ensure wells are spaced in the bank select and column decoder

2018-02-02 15:26:15 -08:00

bitcell_array.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-01-31 17:37:16 -08:00

bitcell.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00

contact.py

Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells.

2018-01-11 10:24:44 -08:00

control_logic.py

Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive.

2018-02-07 14:54:59 -08:00

debug.py

Clean up messages.

2018-01-31 11:54:20 -08:00

delay_chain.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

design.py

Disable virtual connects at top level LVS with Calibre.

2018-02-05 14:52:51 -08:00

example_config_freepdk45.py

Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations.

2018-02-02 19:33:07 -08:00

example_config_scn3me_subm.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

geometry.py

Remove metal3 blanket blockage on library cells.

2017-12-19 09:55:59 -08:00

globals.py

Remove version from OpenRAM. We will go bit git hashes.

2018-02-06 10:56:26 -08:00

hierarchical_decoder.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

hierarchical_predecode2x4.py

Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.

2018-02-02 14:08:56 -08:00

hierarchical_predecode3x8.py

Fix input discrepencies in pre3x8

2018-01-29 15:25:41 -08:00

hierarchical_predecode.py

Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.

2018-02-02 14:08:56 -08:00

hierarchy_layout.py

Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working.

2018-02-05 10:22:38 -08:00

hierarchy_spice.py

Remove level of indirection to ptx devices to allow LVS symmetries.

2018-01-29 15:25:15 -08:00

lef.py

Remove metal3 blanket blockage on library cells.

2017-12-19 09:55:59 -08:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

ms_flop_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

ms_flop.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

openram.py

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

options.py

Add -d option to not delete temp directory on successful runs.

2018-02-01 11:53:02 -08:00

path.py

Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins.

2017-10-05 17:35:05 -07:00

pgate.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

pin_layout.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

pinv.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

pnand2.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

pnand3.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

pnor2.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

precharge_array.py

Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells.

2018-01-11 10:24:44 -08:00

precharge.py

Fix precharge nwell contact spacing DRC violatin.

2018-01-26 13:53:45 -08:00

ptx.py

Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.

2018-02-05 16:02:57 -08:00

regress.sh

Add regress.sh script for convenience

2016-11-18 08:00:34 -08:00

replica_bitcell.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

replica_bitline.py

Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive.

2018-02-07 14:54:59 -08:00

route.py

Fix gnd connection in control logic.

2018-02-02 13:04:38 -08:00

sense_amp_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

sense_amp.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00

single_level_column_mux_array.py

Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.

2018-02-02 15:17:21 -08:00

single_level_column_mux.py

Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module.

2018-02-02 15:17:21 -08:00

sram.py

Disable virtual connects at top level LVS with Calibre.

2018-02-05 14:52:51 -08:00

tri_gate_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

tri_gate.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00

utils.py

Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.

2017-12-12 15:50:45 -08:00

vector.py

Merge master branch into router

2017-01-09 14:04:37 -08:00

verilog.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

wire.py

Fix gnd connection in control logic.

2018-02-02 13:04:38 -08:00

wordline_driver.py

Fix nand input ordering to correct netgen LVS error of wordline driver.

2018-01-29 15:36:37 -08:00

write_driver_array.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-01-31 17:37:16 -08:00

write_driver.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-01-31 17:37:16 -08:00