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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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62439bdac6ede5543d2c38addc98a0f19c8276be
OpenRAM/compiler/characterizer
T
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Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py
2018-10-22 17:29:14 -07:00
..
__init__.py
Added class and test for testing the delay of several bitcells.
2018-10-08 15:50:52 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Cleaned up indexing in variable that records cycle times.
2018-10-10 00:02:03 -07:00
functional.py
Improved debug comments for functional test
2018-10-22 01:09:38 -07:00
lib.py
fixed html typos, added logo, added placeholder timing and current, began ports section
2018-10-17 19:27:09 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
simulation.py
Fixed merge conflicts with sram.py
2018-10-22 17:29:14 -07:00
stimuli.py
Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail.
2018-10-08 06:34:36 -07:00
trim_spice.py
Fixed merge conflicts with sram.py
2018-10-22 17:29:14 -07:00
worst_case.py
Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation
2018-10-09 17:44:28 -07:00
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